Until now, flash memories have been known as a type of nonvolatile memories. A memory cell used in these flash memories has a laminated structure in which a floating gate is formed over a substrate through a tunnel oxide film and a control gate is formed in addition over the substrate through a gate insulating film. The operation principle of this memory cell is briefly explained as follows. During a write operation, electrons (or holes) are injected from a drain to a floating gate using a voltage difference between the control gate and the drain. During an erase operation, electrons (or holes) in the floating gate are released into the drain by a similar voltage control between the control gate and the drain. Assume that the channel is of P-type, and the source and the drain are of n-type. Then, the channel is turned off when electrons are present in the floating gate whereas the channel is turned on when electrons are absent in the floating gate. Accordingly, the memory cell functions as a nonvolatile memory.
Technologies for constructing such a nonvolatile memory with thin film transistors (TFTs) have been disclosed in Paten Document 1, for example. FIG. 14 is a schematic view showing a configuration of a nonvolatile memory (nonvolatile transistor) that is constituted of TFTs in Patent Document 1.
In the nonvolatile transistor shown in FIG. 14, a source region 142A (S), a drain region 142B (D) and a channel region 142C (Ch) are formed in an active region 125B as element regions to function as a transistor. In addition, a floating gate 125A (FG) is formed to face the channel region 142C through a gate insulating film 124B, and a control gate 123 (CG) is formed to face the floating gate 125A through an interlayer insulating film 124A.
Here, the principle of a write operation when the aforementioned nonvolatile transistor is an N channel thin film transistor (N channel TFT) is explained. When data “1” is written into an N channel TFT, the source region 142A is grounded and a high voltage is applied to the drain region 142B and the control gate 123, thereby injecting high-energy electrons (hot electrons) from the drain region 142B to the floating gate 125A. Then, hot electrons are stored in the floating gate 125A and data “1” is written into the N channel TFT.